Hello, and welcome to the TI Precision Lab discussing architectures of high speed A-to-D converter and D-to-A converter devices. First, we will discuss the basic architecture of a flash A-to-D converter stage and then show how that basic stage is used as the core structure in more complex A-to-D converter architectures such as a pipelined A-to-D converter. Interleaved A-to-D converters are discussed as well as successive approximation A-to-D converters. Finally, the basic D-to-A converter core architecture is presented. 

The most basic components of an A-to-D converter is the track and hold stage, also called sample and hold followed by a flash converter stage. The track and hold stage at its most basic consists of a switch controlled by the sample clock and a sampling capacitor to hold the value to be digitized. During the portion of the sample clock when the clock is logic low, the switches close allowing the incoming analog signal to be present on the sampling cap. 

The voltage on the cap will track the incoming signal during the clock low portion, then when the sample clock transitions to a logic high the switch will open. This isolates the sampling cap from the incoming analog signal, so that the cap holds the voltage at the instant the switch is opened, thus the name track and hold circuit. While the incoming signal has been frozen on the sampling cap, the digitizer stage has half a clock period to transform the capacitor voltage to a digital code before the switch closes again, and the device enters the track stage again. 

The illustration shows a simple 3-bit flash conversion stage. To digitize the signal to a 3-bit code, it would require 2 to the n minus 1 voltage comparators or seven comparators. The voltage comparators are arranged with a series of threshold voltages with the voltage to be converted being input to each of the comparators. If the analog input voltage is higher than the lowest threshold voltage, then the comparator output is active. If the voltage is higher than the second threshold voltage, then that comparator is active. If the voltage is higher than the third threshold, then that comparator is active and so on. 

After the seven comparators, there will be a set of 7 results of the comparators often called a thermometer code. This is because as the input voltage rises and falls, the number of outputs active rises and falls somewhat like a thermometer. At this point, the thermometer code is a digital representation of the input signal, but it is more common to have some digital logic to convert the thermometer code into an arithmetic code. 

Finally, there remains the task of latching the arithmetic code into a register on the falling edge of the sample clock to catch the sample before the signal held on the cap begins to change again. A flash converter stage requires 2 to the n minus 1 voltage comparators which is reasonable for data converters of resolution of 5 or 6 bits. A 6-bit flash A-to-D converter would require 63 voltage comparators. This concept would not be practical for extensions through 12 or 14-bit A-to-D converters. A 14-bit flash A-to-D converter would require 16,535 voltage comparators. Even if this were reasonable to implement on a chip, the difference between adjacent threshold voltages could be smaller than the inherent offset error voltage of the comparators causing core linearity or even missing output codes. 

If a flash A-to-D converter stage is limited to 5 or 6 bits, then a higher precision data converter could be implemented in pipeline stages. A 14-bit A-to-D converter implemented in 3 pipeline stages is illustrated here. The first A-to-D converter stage is a 5-bit flash stage yielding a 5-bit resolution of the sample. But when this 5-bit sample is latched, the 5-bit code is converted back to an analog voltage by a matching internal 5-bit D-to-A converter. 

At this point, we have the actual input voltage with its 5-bit code that represents that voltage and an ideal voltage that corresponds to the 5-bit code. The difference between the actual input voltage and the ideal voltage assigned to that code is called the residue or the quantization error between the actual voltage and the ideal voltage. But if we multiply this residue by a factor of 32 after a 5-bit flash A-to-D stage, then the residue is expanded out to the original full-scale range of the A-to-D converter. Then this residue can be further quantized by a second flash A-to-D converter stage to gain more precision in the resulting sample. 

This cascade of pipeline stages could in theory be extended forever to gain unlimited resolution of the sample. But in practice, small mismatches and gain between the different A-to-D converter stages, DAC stages and residue amplifiers will lead to a buildup of error, three or four pipeline stages are commonly feasible depending on the accuracy of trimming the tolerances of all the individual components. Finally, there is commonly one bit of overlap designed into the pipeline stages so that a slight mismatch between an A-to-D converter stage and its following DAC stage doesn't lead to a jump in the output code that might be larger than one least significant bit of the final code. 

This bit of overlap is resolved with arithmetic logic as the pieces from the individual stages are combined into a complete sample. In the example here, the first stage provides 5 bits of resolution, while the second stage provides an additional 4 bits of resolution, and the final stage provides an additional 5 bits of resolution for a final sample of 14 bits. 

Another approach to higher resolution conversion is the successive approximation A-to-D converter. In this architecture, the analog input signal is also frozen in a sample and hold or track and hold circuit as was used in the flash or pipelined A-to-D converter, but after the input signal is being held by the track and hold circuit, the method of converting this voltage to a digital code is different. In this approach, the A-to-D converter iteratively adds a bit of resolution per iteration until the desired number of bits have been derived. A single comparator is used, but with a D-to-A converter stage to iteratively generate a succession of threshold voltages. 

The first threshold voltage determines the most significant bit of the sample comparing if the input voltage is above or below mid-scale. If it is above mid-scale, the most significant bit is one, and the D-to-A converter moves on to the next threshold voltage, which would be halfway between mid-scale and full scale. After the desired number of bits have been derived, the sample is output with a signal for end of conversion. 

One disadvantage of this approach is that the maximum conversion rate is limited by the speed of the D-to-A converter plus comparator divided by the number of bit iterations that must be performed. Thus, this architecture is most often used for relatively low speed and low power but higher resolution A-to-D converters. Commonly, 16 or 18 bits or even more are implemented. 

For a single pipelined A-to-D converter, the maximum sample rate will be largely limited by the time for the flash A-to-D converter stage to settle, and get its output latched in half a clock cycle. One common way to achieve higher sample rates is to use multiple A-to-D converter stages in parallel with the clocking delayed and staggered. Benefits are a much higher achievable sample rate than can be achieved with a single A-to-D converter for a given process node. 

Drawbacks include the requirement to distribute the input signal to all interleaved A-to-D converters without skew or amplitude mismatches and increase loading and distribution burdens on the analog input signal and the clock distribution. Mismatches in clocking or analog signal distribution will lead to distortions in the sample data and loss of performance. 

Common sources of errors in interleaved A-to-D converters include offset mismatch, amplitude mismatch, and clock phase mismatch. Offset mismatch and gain mismatch are relatively easy to correct for by way of digital logic operating on the sample data stream following the interleaved sub A-to-D converter. Digital logic could be designed to generate an estimate of offset mismatch and or gain mismatch from the sample data from each interleaved sub A-to-D converter. Then the estimated offset error could be subtracted from the sample data in real time with arithmetic logic. 

Likewise, the estimated gain error could be used to compensate the sample data in real time with multiplication logic. Phase error compensation is more difficult to correct in real time. Offset error is due to different DC offset voltages for the different interleaved A-to-D converter cores in a design. In this example, the red waveform is the waveform as seen by one interleaved A-to-D converter while the green waveform is the waveform as seen by the other interleaved A-to-D converter. 

For uncorrected offset error, the result of the error has the appearance of a sawtooth pattern on top of the ideal sample pattern with samples ultimately higher or lower in value than ideal. In the frequency domain, this tends to look like spurs in the resulting FFT spectrum at the Nyquist rate or sample rate over 2 for two-way interleaving or multiples of sample rate over 4 for four-way interleaving. 

Gain error is due to different gain values for the different interleaved A-to-D converter cores in a design. In this example, the red waveform is the waveform as seen by one interleaved A-to-D converter while the green waveform is the waveform as seen by the other interleaved A-to-D converter. Uncorrected gain error also gives rise to a sawtooth appearance on the sample data as was the case with offset error but with the difference that the direction of the error inverts as it crosses mid-scale. 

In the above example where the red waveform is reduced in gain, above mid-scale the sample is lower than the ideal code, and below mid-scale the sample is higher than the ideal code. The resulting spectrum is more complicated than that of the simple offset error with repeating images dependent on the frequency of the input signal. In the sketch of spectrum shown, the repeating images of the input signal is shown as well as repeating images of the second harmonic of the input signal. 

There are a range of options for how to deal with mismatches in interleaved systems. For applications requiring higher sample rate with less emphasis on performance, interleaving that relies on matching of external factors such as length of signal routing to the A-to-D converters might be adequate. To maintain AC performance in terms of signal-to-noise ratio or harmonic performance, it may be necessary to perform some kind of interleaving correction. This generally involves some method to estimate the magnitude of the mismatch and then some manner of correcting for the mismatch. 

The correction could be applied to the analog signal prior to the sampling or applied digitally to the sample data after conversion. The estimation function could be performed at one time initially in which case the estimate would not account for drifting of environmental conditions such as temperature unless a recalibration were to be performed at certain intervals. The estimation function may be performed continuously on a sliding window of sample data during normal operation of the A-to-D converter. One drawback of most estimation algorithms used to estimate gain or offset mismatch is the possibility of a pathological input pattern that performs poorly for the estimation algorithm employed. 

Digital-to-analog conversion is not simply the opposite of analog-to-digital conversion. The simplest architecture for a D-to-A converter is the current steering circuit. The D-to-A converter is designed to move a certain amount of current into or out of a load. And Ohm's law relates this current to the output voltage. In this example, if the full scale output of D-to-A converter is 30 milliamps into a 50 ohm load, then the full-scale output voltage would be 1.5 volts single-ended or 3.0 volt peak-to-peak differential in the above example. Current-steering D-to-A converters could be of the current sink or the current source type. The difference is in whether the D-to-A converter current source is from the DAC supply through the load resistor to ground or from the external pull-up supply through the load resistor and then sinking to ground through the D-to-A converter. 

A current source D-to-A converter would typically be designed with P-channel devices for the current source while a current sync data A-converter would typically be designed with N-channel transistors. In either case, the output voltage would be determined by Ohm's law considering the amount of current through the load resistor. 

Whether current source or current sync, one approach would be to implement the D-to-A converter output stage as a parallel combination of current mode drivers with the current capability of each driver scaled by a power of 2 compared to the adjacent drivers. In this simple 3-bit example, the driver for the most significant bit has a current capacity of 500 micro amps while the next bit has a capacity of 250 micro amps and 125 micro amps for the least significant bit. The full scale output would be with all three drivers active for a current of plus or minus 875 microvolt. 

The advantage of this approach is that for a resolution of N bits, only N output drivers need to be designed to output in parallel. The disadvantage is that matching the output drivers is difficult to achieve for larger bit counts as the tolerance of the most significant bit could possibly swamp that of the resolution intended for the least significant bit. Unless the tolerance of the proper power of two scaling from the most significant bit down to the least significant bit is held, the linearity of the D-to-A converter would suffer. 

Another approach to the D-to-A converter current output is to make the output drivers matched in current capacity. In this approach, it is easier to hold the tolerances of the output drivers to achieve good matching from one driver to the next, but there would now need to be 2 to the N minus 1 output drivers for N bits of resolution. The example 3-bit D-to-A converter shown would require seven output drivers of equal current capacity. Full scale output would require all drivers to be active in parallel. 

In this case, the input sample code would be converted from an arithmetic code to a thermometer code and each bit of the thermometer code would control an individual output driver. Better matching can be achieved across the output drivers in the structure, but for high resolution samples, the number of drivers to implement becomes prohibitive. A 14-bit D-to-A converter would require 16,535 output drivers in parallel. 

To achieve a higher resolution D-to-A converter, a combination of the binary D-to-A converter and thermometer code D-to-A converter may be employed. In this example, a 6-bit D-to-A converter may use the upper three bits of the sample to control a thermometer coded D-to-A converter, so that there need only be seven matched current drivers in parallel. Then the lower 3-bits may be used to control three more current drivers that are scaled by powers of two in size. In this way, the matching of the current scaling only has to span 2 to the power of 4. Higher resolution D-to-A converters such as 14 to 16 bits would likely be implemented by this mix of coding styles. 

For a 16-bit D-to-A converter example, the upper six bits of the sample are converted into a 63-bit thermometer code to drive 63 matched current sources. At the same time, the lower 10 bits of the sample are used directly to drive 10 scaled current sources also in parallel with the 63 matched current sources. Thus, the total number of current drivers is 73, and the matching of the scaled binary current drivers must be matched well across a span of 2 to the power of 11. That is, the 10 binary drivers are scaled across the span of 2 to the power of 10, but the thermometer coded drivers are all two times the size of the largest of the scale drivers. This concludes this video. Thank you for watching.