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Today, I would like to introduce noise and how it relates to linear regulators and LDOs. First of all, to clarify, noise is not PSRR. PSRR, or power supply ripple rejection, is covered in another video. But in simple terms, PSRR is a measure of how well the regulator attenuates the noise at the input. Noise is what comes out of the LDO. Electronic noise is inherent in all semiconductors and is typically expressed in terms of microvolts per square root Hertz. 

LDO's generate noise. While ideally, we would like to say they do not, all electronics are guilty of generating noise. You can't really get a feel for noise using an oscilloscope in a time domain, as what you will see is just noise. This gives you no understanding as to where the noise may impact your application. 

To see how noise impacts a system, a spectrum analyzer can help show where the noise is really impacting your application. By using a spectrum analyzer, you can see the noise across a wide frequency range. This plot shows the noise spectrum from 10 hertz on to 10 megahertz, and how increasing Vout increases the noise. We think showing noise in this fashion is more meaningful than simply providing a number in terms of microvolt RMS. While that number makes it easy to compare, seeing the full spectrum over the output voltage is a clearer way to understand how noise impacts the application. 

So now that we know noise exists and increases as a function of Vout, how do we reduce it? Well, the first step is to make sure you select a low-noise LDO. This is not easy, as some LDOs claim to be low noise, but offer literal or no information as to how low the noise is. Often, low-noise LDOs have an external NR/SS, or noise reduction/soft-start capacitor. 

Normally, a noise reduction capacitor has two functions. The first is to filter out the band-gap noise. The second is to provide a soft-start ramp. Note, this effect is minimal if the LDO has a quick-start circuit. This plot shows how adding a noise reduction capacitor can help to reduce noise. The example here is using the TPS7A90. 

This plot shows how increasing the noise reduction capacitor from 0 to 100 nanofarads changes the rise time of Vout from near-instantaneous to taking over 15 milliseconds to rise. The inrush current can be modeled as a function of the total amount of capacitance at the output of the LDO and the rate of change of the output voltage. 

The final step to reduce noise with an LDO is to add a CFF, or a feed-forward capacitor. As you can see here in this example, adding a 100-nanofarad capacitor can reduce the noise by up to 45%. Adding a feed-forward capacitor has the following advantages-- first, the improved noise performance, second, it provides a faster load transient response, and third, last but not least, it improves PSRR as shown in the PSRR basics video. 

In summary, to minimize noise in the application-- step one, choose a low-noise LDO. Step 2, add a noise reduction capacitor, as this improves noise content in the low- to mid-frequency range. Step 3, add a feed-forward capacitor to improve noise across the frequency range, with the biggest impact being from 1 kilohertz to 100 kilohertz. 

[GENTLE WHOOSH] 

Well, thanks for watching. For more information, please visit ti.com/ldo, where we have a lot more information and a quick search tool for helping you find the optimal LDO for your application. Additionally, we have access to videos, blogs, application notes, and most importantly, online support with our E2E forum. 

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